Within the Data Acquisition (DAQ) system of the 1 Mpixel camera based on DEPFET Sensor with Signal Compression (DSSC) at the European X rays-Free Electron Laser (EuXFEL), the DEPFETs are read-out by two Field-Programmable Gate Array (FPGA) stages: the Input Output Board (IOB), which currently houses an End-of-Life (EoL) low-area and low-power Xilinx 45-nm 6-Series Spartan-6 (i.e., XC6LX45T), and the Patch Panel Transceiver (PPT) with an high-performance Xilinx 28-nm 7-Series Kintex-7 device. The IOB is the first acquisition stage located near the detector, housed within a vacuum-sealed metallic container, and operates at low temperature (i.e., -20°C). This specific working environment imposes significant constraints on the physical size of the board and compliance with thermal and current budgets. At EuXFEL a new detector development program is in the definition phase. This paper reports feasibility studies performed on the IOB, in order to provide, on one side spare parts for the existing installed detectors, and on the other, to check which kind of system could be compatible also for future operation. It is necessary to begin with a redesign of the IOB because the Spartan-6 FPGA it hosts is at End-of- Life (EOL). Moreover, using newer and more advanced FPGAs makes it natural to introduce features that can be compatible with future upgrades of the detectors at the European XFEL; e.g., higher pixel count, self-trimming, and pre-calibration. In this regard, two different models of Xilinx FPGAs at 16 nm, the SU65P Spartan UltraScale+ and the AU15P Artix UltraScale+, compatible with the current Spartan-6 in terms of package size, number of I/Os, amount of logic, and availability of transceivers, have been selected. This preliminary analysis covers aspects related to the estimation of resource usage, power consumption, operating frequency, and bandwidth, considering the current Spartan-6 FPGA and its firmware as reference.
Study for the Upgrade of the Front-End DAQ of the DSSC Megapixel Camera for a Potential New Generation of Detectors at the European XFEL
Porro, M.
2024-01-01
Abstract
Within the Data Acquisition (DAQ) system of the 1 Mpixel camera based on DEPFET Sensor with Signal Compression (DSSC) at the European X rays-Free Electron Laser (EuXFEL), the DEPFETs are read-out by two Field-Programmable Gate Array (FPGA) stages: the Input Output Board (IOB), which currently houses an End-of-Life (EoL) low-area and low-power Xilinx 45-nm 6-Series Spartan-6 (i.e., XC6LX45T), and the Patch Panel Transceiver (PPT) with an high-performance Xilinx 28-nm 7-Series Kintex-7 device. The IOB is the first acquisition stage located near the detector, housed within a vacuum-sealed metallic container, and operates at low temperature (i.e., -20°C). This specific working environment imposes significant constraints on the physical size of the board and compliance with thermal and current budgets. At EuXFEL a new detector development program is in the definition phase. This paper reports feasibility studies performed on the IOB, in order to provide, on one side spare parts for the existing installed detectors, and on the other, to check which kind of system could be compatible also for future operation. It is necessary to begin with a redesign of the IOB because the Spartan-6 FPGA it hosts is at End-of- Life (EOL). Moreover, using newer and more advanced FPGAs makes it natural to introduce features that can be compatible with future upgrades of the detectors at the European XFEL; e.g., higher pixel count, self-trimming, and pre-calibration. In this regard, two different models of Xilinx FPGAs at 16 nm, the SU65P Spartan UltraScale+ and the AU15P Artix UltraScale+, compatible with the current Spartan-6 in terms of package size, number of I/Os, amount of logic, and availability of transceivers, have been selected. This preliminary analysis covers aspects related to the estimation of resource usage, power consumption, operating frequency, and bandwidth, considering the current Spartan-6 FPGA and its firmware as reference.
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