Hardware execution of constraint handling rules

In this thesis we want to investigate the compiling of the well-established language Constraint Handling Rule (CHR) to a low level hardware description language (HDL). The benefit introduced by a CHR-based hardware synthesis is twofold: it increases the abstraction level of the common synthesis work-flow and it can give significant speed up to the execution of a CHR program in terms of computational time. We want to propose a method that sets CHR as a starting point for a hardware description. The developed hardware will be able to turn all the intrinsic concurrency of the language into parallelism. The rules application is mainly achieved by a custom executor that handles constraints according to the best degree of parallelism the implemented CHR specification can offer. Afterwards we want to integrate the generated hardware code, deployed in a Field Programmable Gate Array (FPGA), within the traditional software execution model of CHR. The result will be a prototype system consisting of a CHR execution engine composed of a general purpose processor coupled with a specialized hardware accelerator. The former will execute a CHR specification while the latter will unburden the processor by executing in parallel the most computational intensive rules. Finally the performance of the proposed system architecture will be validated by time efficiency measures.