We present the initial concept of XAPPHIRE, a detector platform proposed for the European XFEL. The goal is to cover the diverse needs of future experiments-from sub-keV soft X-rays to >20keV hard X-rays-by realising only a few detector variants built on one shared architecture. Core parameters such as pixel pitch (≤100μ m), MHz-rate acquisition, and the ability to read pulse trains of variable length are fixed; only elements that truly drive performance (mainly the sensor and first analogue stage) differ between variants. For soft X-rays, candidate sensors include standard diodes, MiniSDDs, DEPFETs, and LGADs, while hard-X-ray operation relies on thick silicon diodes, with high-Z materials under evaluation. The read-out ASICs will maximise block reuse: optimum analogue filtering, ADCs, on-chip SRAM for burst readout where needed, and high-speed serializers, all implemented in a scaled CMOS node (≤28 nm). Alongside that burst-readout chain, a continuous-readout option that omits local SRAM in favour of an even faster serializer is being explored, targeting frame rates up to 1 Mframe/s. We outline the architectural principles, the criteria for selecting a baseline design, and the planned next steps-from concept validation to first prototypes and full system-level demonstrators.
XAPPHIRE: A Unified Detector Platform for Soft- and Hard-X-Ray Imaging
Porro, M.
;
2025
Abstract
We present the initial concept of XAPPHIRE, a detector platform proposed for the European XFEL. The goal is to cover the diverse needs of future experiments-from sub-keV soft X-rays to >20keV hard X-rays-by realising only a few detector variants built on one shared architecture. Core parameters such as pixel pitch (≤100μ m), MHz-rate acquisition, and the ability to read pulse trains of variable length are fixed; only elements that truly drive performance (mainly the sensor and first analogue stage) differ between variants. For soft X-rays, candidate sensors include standard diodes, MiniSDDs, DEPFETs, and LGADs, while hard-X-ray operation relies on thick silicon diodes, with high-Z materials under evaluation. The read-out ASICs will maximise block reuse: optimum analogue filtering, ADCs, on-chip SRAM for burst readout where needed, and high-speed serializers, all implemented in a scaled CMOS node (≤28 nm). Alongside that burst-readout chain, a continuous-readout option that omits local SRAM in favour of an even faster serializer is being explored, targeting frame rates up to 1 Mframe/s. We outline the architectural principles, the criteria for selecting a baseline design, and the planned next steps-from concept validation to first prototypes and full system-level demonstrators.I documenti in ARCA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.



