The 64k pixel DEPFET module is the key sensitive component of the DEPFET Sensor with Signal Compression (DSSC), a large area 2D hybrid detector for capturing and measuring soft X-rays at the European XFEL. The final 1-megapixel camera has to detect photons with energies between 250eV and 6keV , and must provide a peak frame rate of 4.5MHz to cope with the unique bunch structure of the European XFEL. This work summarizes the functionalities and properties of the first modules assembled with full-format CMOS-DEPFET arrays, featuring 512×128 hexagonally-shaped pixels with a side length of 136 μm. The pixel sensors utilize the DEPFET technology to realize an extremely low input capacitance for excellent energy resolution and, at the same time, an intrinsic capability of signal compression without any gain switching. Each pixel of the readout ASIC includes a DEPFET-bias current cancellation circuitry, a trapezoidal-shaping filter, a 9-bit ADC and a 800-word long digital memory. The trimming, calibration and final characterization were performed in a laboratory test-bench at DESY. All detector features are assessed at 18°C . An outstanding equivalent noise charge of 9.8 e−rms is achieved at 1.1-MHz frame rate and gain of 26.8 Analog-to-Digital Unit per keV (ADU/keV). At 4.5MHz and 3.1ADU/keV , a noise of 25.5 e−rms and a dynamic range of 26ke- are obtained. The highest dynamic range of 1.345Me- is reached at 2.25MHz and 1.6ADU/keV . These values can fulfill the specification of the DSSC project

A 64k pixel CMOS-DEPFET module for the soft X-rays DSSC imager operating at MHz-frame rates

Porro, Matteo
2023-01-01

Abstract

The 64k pixel DEPFET module is the key sensitive component of the DEPFET Sensor with Signal Compression (DSSC), a large area 2D hybrid detector for capturing and measuring soft X-rays at the European XFEL. The final 1-megapixel camera has to detect photons with energies between 250eV and 6keV , and must provide a peak frame rate of 4.5MHz to cope with the unique bunch structure of the European XFEL. This work summarizes the functionalities and properties of the first modules assembled with full-format CMOS-DEPFET arrays, featuring 512×128 hexagonally-shaped pixels with a side length of 136 μm. The pixel sensors utilize the DEPFET technology to realize an extremely low input capacitance for excellent energy resolution and, at the same time, an intrinsic capability of signal compression without any gain switching. Each pixel of the readout ASIC includes a DEPFET-bias current cancellation circuitry, a trapezoidal-shaping filter, a 9-bit ADC and a 800-word long digital memory. The trimming, calibration and final characterization were performed in a laboratory test-bench at DESY. All detector features are assessed at 18°C . An outstanding equivalent noise charge of 9.8 e−rms is achieved at 1.1-MHz frame rate and gain of 26.8 Analog-to-Digital Unit per keV (ADU/keV). At 4.5MHz and 3.1ADU/keV , a noise of 25.5 e−rms and a dynamic range of 26ke- are obtained. The highest dynamic range of 1.345Me- is reached at 2.25MHz and 1.6ADU/keV . These values can fulfill the specification of the DSSC project
2023
13
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10278/5035934
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