We propose a CMOS circuit designed to be used with silicon drift detectors (SDDs) for high-resolution and high peak stability X-ray spectroscopy. The circuit is developed in the framework of a project for researches on 'exotic atoms' (e.g. kaonic hydrogen) at e/sup -//e/sup +/ colliders. The circuit is composed by a low-noise charge preamplifier and by a 6th order semiGaussian shaping amplifier with four selectable peaking times from 0.7 /spl mu/s up to 3 /spl mu/s. The preamplifier operates with the input JFET directly integrated on the detector itself. A low-frequency current-mode feedback loop allows to stabilize the operating point of the input JFET with respect to background and leakage current variations. The feedback capacitor is integrated on the detector and its value is not known precisely in advance. The preamplifier is designed with the possibility to adjust externally its decay time to match the fixed time constant of the pole/zero network. A baseline holder senses the baseline voltage shifts at the output of the circuits due to the DC changes of the drain voltage of the input JFET in correspondence of background variations and provides a feedback loop back to the preamplifier to stabilize the output baseline. A bipolar shaping provides a timing signal required by the experiment. A first prototype has been realized in the 0.35 /spl mu/m AMS technology. The energy resolution measured using the chip with a SDD of 5 mm/sup 2/ is of 137 eV at 6 keV (ENC = 8e/sup -/ rms).

A CMOS circuit for high-stability X-ray Spectroscopy with Silicon Drift Detectors with on-chip JFET

Porro M.
2005-01-01

Abstract

We propose a CMOS circuit designed to be used with silicon drift detectors (SDDs) for high-resolution and high peak stability X-ray spectroscopy. The circuit is developed in the framework of a project for researches on 'exotic atoms' (e.g. kaonic hydrogen) at e/sup -//e/sup +/ colliders. The circuit is composed by a low-noise charge preamplifier and by a 6th order semiGaussian shaping amplifier with four selectable peaking times from 0.7 /spl mu/s up to 3 /spl mu/s. The preamplifier operates with the input JFET directly integrated on the detector itself. A low-frequency current-mode feedback loop allows to stabilize the operating point of the input JFET with respect to background and leakage current variations. The feedback capacitor is integrated on the detector and its value is not known precisely in advance. The preamplifier is designed with the possibility to adjust externally its decay time to match the fixed time constant of the pole/zero network. A baseline holder senses the baseline voltage shifts at the output of the circuits due to the DC changes of the drain voltage of the input JFET in correspondence of background variations and provides a feedback loop back to the preamplifier to stabilize the output baseline. A bipolar shaping provides a timing signal required by the experiment. A first prototype has been realized in the 0.35 /spl mu/m AMS technology. The energy resolution measured using the chip with a SDD of 5 mm/sup 2/ is of 137 eV at 6 keV (ENC = 8e/sup -/ rms).
IEEE Nuclear Science Symposium Conference Record, 2005
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10278/5008948
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