The PPT-module: High-performance readout for the DSSC detector at XFEL

DSSC is one of several 2D megapixel detectors currently being built for the European XFEL at DESY, Hamburg. DSSC acquires 8-bit digitized image-series of 700 frames at a sample rate of 4.5MHz. Repetition rate is 10Hz. Non-linear sensor characteristics improves the low-energy resolution. DSSC readout operation involves several subsystems: overall clock and timing control distributed from the XFEL machine via a few dedicated signals. Slow- control and back-end data acquisition controlled via a control Ethernet network. Back-end data acquisition is composed of a computing farm and a train-builder unit, which collects data in detector-specific formats and provides frames in a common format to the back-end. The PPT module is located at the external boundary of the detector, interfacing to both the external subsystems and the on-detector readout module (IOB). The IOB controls the primary readout ASICs and combines the parallel input channels into fewer high-speed serial links towards the PPT. The PPT has to provide the intelligent control of the DSSC instrument. At the same time it handles the readout data from four IOBs: receiving over twelve 3Gbit/s links, reformatting and buffering into a DDR3-memory buffer and transmitting UDP packets over four 10Gbit/s links towards the train-builder. The nominal payload bandwidth is in the order of 4*9Gbit/s. The implementation is based upon state-of-the art FPGA technology using a Xilinx Kintex-7 device. The control portion of the design executes on an embedded Linux system running on a Microblaze processor inside the FPGA. The data-path portion is implemented by a number of VHDL-modules. The UDP output is driven by a complex multi-channel DMA engine under control of the processor. We present the first measurements from the data handling performance, the operation of the interface to the external timing and control system and the control software.