This work presents the experimental results from the characterization of the second prototype of a high accuracy (in terms of linearity, mismatch and noise) injection circuit to be used for in-pixel calibration of a large sensor matrix. The circuit was designed for the calibration of the pixel cell unit of a hybrid pixel device, the DEPFET Sensor with Signal Compression (DSSC) chip, for the large format imager at the European X-ray Free Electron Laser (XFEL), but, in principle, it can be used also for other kinds of detectors, e.g., deep N-well monolithic CMOS sensors. In the case of hybrid pixels, the injection circuit is particularly useful to test the functionality of the readout electronics already at the chip level, when no sensor is connected to the chip. Two injection techniques have been investigated: one for a charge sensitive amplification and the other for a transresistance readout channel. The aim of the paper is to describe the architecture of the calibration circuit, which has been implemented in a 130-nm CMOS technology, and to present the results from the characterization of the second prototype. © 1963-2012 IEEE.

Pixel-level charge and current injection circuit for high accuracy calibration of the dssc chip at the european xfel

Porro M.
2013-01-01

Abstract

This work presents the experimental results from the characterization of the second prototype of a high accuracy (in terms of linearity, mismatch and noise) injection circuit to be used for in-pixel calibration of a large sensor matrix. The circuit was designed for the calibration of the pixel cell unit of a hybrid pixel device, the DEPFET Sensor with Signal Compression (DSSC) chip, for the large format imager at the European X-ray Free Electron Laser (XFEL), but, in principle, it can be used also for other kinds of detectors, e.g., deep N-well monolithic CMOS sensors. In the case of hybrid pixels, the injection circuit is particularly useful to test the functionality of the readout electronics already at the chip level, when no sensor is connected to the chip. Two injection techniques have been investigated: one for a charge sensitive amplification and the other for a transresistance readout channel. The aim of the paper is to describe the architecture of the calibration circuit, which has been implemented in a 130-nm CMOS technology, and to present the results from the characterization of the second prototype. © 1963-2012 IEEE.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10278/3755455
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