We report on the fabrication and electrical characterization of ferroelectric FETs (Fe-FET) on fully depleted SOI. The transistor gate stack is made by a 45nm P(VDF-TrFE) 70%-30% layer on top of 10nm thermal SiO2. The improved junction leakage control in thin SOl enables the accurate investigation of the electrical DC characteristics of Fe-FETs in a range of temperature from 25°C up to 90°C. Reductions of the non-saturated hysteretic loop and of lon/Ioff are observed at high temperature but the Fe-FET remarkably maintains basic switch functionality with Ion/Ioff> 105 up to 85°C. We particularly report and explain the parabolic dependence of the SOl Fe-FET subthreshold swing, SS, on the temperature, featuring an experimental minimum. ©2009 IEEE.

An experimental study of temperature influence on electrical characteristics of ferroelectric P(VDF-TrFE) FETs on SOI

Salvatore G. A.;
2009-01-01

Abstract

We report on the fabrication and electrical characterization of ferroelectric FETs (Fe-FET) on fully depleted SOI. The transistor gate stack is made by a 45nm P(VDF-TrFE) 70%-30% layer on top of 10nm thermal SiO2. The improved junction leakage control in thin SOl enables the accurate investigation of the electrical DC characteristics of Fe-FETs in a range of temperature from 25°C up to 90°C. Reductions of the non-saturated hysteretic loop and of lon/Ioff are observed at high temperature but the Fe-FET remarkably maintains basic switch functionality with Ion/Ioff> 105 up to 85°C. We particularly report and explain the parabolic dependence of the SOl Fe-FET subthreshold swing, SS, on the temperature, featuring an experimental minimum. ©2009 IEEE.
2009
ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10278/3745814
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