This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60mV/decade subthreshold swing limit at room temperature of MOSFET. We find sub-threshold swings as low as 13mV/decade in Fe-FETs with 40nm P(VDF- TrFE)/SiO2 gate stack. The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that provides voltage amplification; with our particular ferroelectric gate stack we report for the first time negative capacitance at room temperature.

Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack

Salvatore G. A.;
2008-01-01

Abstract

This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60mV/decade subthreshold swing limit at room temperature of MOSFET. We find sub-threshold swings as low as 13mV/decade in Fe-FETs with 40nm P(VDF- TrFE)/SiO2 gate stack. The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that provides voltage amplification; with our particular ferroelectric gate stack we report for the first time negative capacitance at room temperature.
2008
Technical Digest - International Electron Devices Meeting, IEDM
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10278/3745808
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